1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices including alumina (Al2O3) layers and polysilicon or silicon dioxide (SiO2) layers placed thereunder. The method includes steps of selectively processing these layers.
2. Description of the Related Art
Al2O3 that is a high-K material is used to manufacture fine semiconductor devices. In particular, Al2O3 is used to form insulating layers placed between control gates and floating gates included in flash devices. The two types of gates are made of polysilicon and isolated from each other. In order to manufacture the flash devices, polysilicon layers for forming the control and floating gates and the Al2O3 insulating layers are selectively etched because there are steps due to the floating gates and isolation.
Known insulating layers placed between the control gates and the floating gates have an oxide-nitride-oxide (ONO) structure and are etched with CF gas. Since high-integrated, high-speed devices have been demanded, insulating layers having a high dielectric constant are necessary; hence, a high-K material is used to form such insulating layers.
With reference to FIG. 4, a wafer (sample) for manufacturing flash devices includes a silicon substrate 206 having isolation trenches 207 filled with SiO2; base insulating layers 205, arranged on the silicon substrate 206, containing SiO2; first polysilicon layers 204, each placed on the corresponding base insulating layers 205, for forming floating gates; an interlayer insulating layer 203, placed over the first polysilicon layers 204, containing Al2O3; a second polysilicon layer 202, placed on the interlayer insulating layer 203, for forming control gates; and a hard mask 201 placed on the second polysilicon layer 202. The floating gates are formed in such a manner that the first polysilicon layers 204 are etched such that the isolation trenches 207 and the base insulating layers 205 are exposed.
As shown in a sectional view taken along the line A-A in FIG. 4, portions of the second polysilicon layer 202 each make contact with corresponding sections of the interlayer insulating layer 203 that are located on the isolation trenches 207. As shown in a sectional view taken along the line B-B in FIG. 4, other portions of the second polysilicon layer 202 each make contact with corresponding sections of the interlayer insulating layer 203 that lie over the base insulating layers 205 and the first polysilicon layers 204.
Therefore, the second polysilicon layer 202 and the interlayer insulating layer 203 containing Al2O3 must be selectively etched as shown in the sectional view taken along the line B-B.
For example, Japanese Unexamined Patent Application Publication No. 5-160084 discloses that gas containing BCl3 is used to remove alumina deposits from contact holes.
Furthermore, Japanese Unexamined Patent Application Publication No. 2003-318371 discloses that PZT is etched with BCl3 or Ar at high temperature such that the selectivity of a hard mask is increased.
Al2O3 is usually etched with gas containing Cl2 or BCl3. However, such gas has low selectivity for polysilicon and SiO2. Therefore, if the gas is used, the following problem occurs: a problem that the first polysilicon layers 204 and the base insulating layers (gate oxide layers) 205 placed thereunder are etched during the removal of Al2O3 present around steps.